tx_dp_ram Project Status (09/28/2010 - 13:56:38)
Project File:	tx_dp_ram.xise	Parser Errors:	No Errors
Module Name:	tx_dp_ram	Implementation State:	Synthesized (Failed)
Target Device:	xc6vlx240t-1ff1156	Errors:
Product Version:	ISE 12.2	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:	System Settings	Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Tue 28. Sep 13:56:38 2010
Translation Report	Out of Date	Tue 28. Sep 11:15:09 2010
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 09/28/2010 - 13:56:38